P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 12/13/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.1. Endpoint Testbench

The example design and testbench are dynamically generated based on the configuration that you choose for the P-Tile IP for PCIe. The testbench uses the parameters that you specify in the Parameter Editor in Intel® Quartus® Prime.

This testbench simulates up to a ×16 PCI Express link using the serial PCI Express interface. The testbench design does allow more than one PCI Express link to be simulated at a time. The following figure presents a high level view of the design example.

Figure 61. Design Example for Endpoint Designs

The top-level of the testbench instantiates the following main modules:

  • altpcietb_bfm_rp_gen4_x16.sv —This is the Root Port PCIe* BFM.
    //Directory path
  • pcie_ed_dut.ip: This is the Endpoint design with the parameters that you specify.
    //Directory path
  • pcie_ed_pio0.ip: This module is a target and initiator of transactions for the PIO design example.
    //Directory path
  • pcie_ed_sriov0.ip: This module is a target and initiator of transactions for the SR-IOV design example.
    //Directory path

In addition, the testbench has routines that perform the following tasks:

  • Generates the reference clock for the Endpoint at the required frequency.
  • Provides a PCI Express reset at start up.

The SR-IOV design example testbench supports up to two Physical Functions (PFs) and 32 Virtual Functions (VFs) per PF.

For more details on the PIO design example testbench and SR-IOV design example testbench, refer to the Intel FPGA P-Tile Avalon® streaming IP for PCI Express Design Example User Guide.

Note: By default, the serial_sim_hwtcl parameter in <project_dir>/intel_pcie_ptile_ast_0_example_design/pcie_ed_tb/ip/pcie_ed_tb/dut_pcie_tb_ip/intel_pcie_ptile_tbed_<ver>/sim/intel_pcie_ptile_tbed_hwtcl.v is set to 1 for serial simulation. P-Tile does not support parallel PIPE simulations.