P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 12/13/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Interface Reset Signals

Table 47.  Interface Reset Signals
Signal Name Direction Clock EP/RP/BP Description
pin_perst_n Input Asynchronous EP/RP/BP This is an active-low input to the PCIe* Hard IP, and implements the PERST# function defined by the PCIe* specification.
p<n>_pin_perst_n where n = 0, 1, 2, 3 Output Asynchronous EP/RP/BP This is the PERST output signal from the Hard IP. It is derived from the pin_perst_n input signal.
p<n>_reset_status_n where n = 0, 1, 2, 3 Output Synchronous to coreclkout_hip EP/RP/BP This active-low signal is held low until pin_perst_n has been deasserted and the PCIe* Hard IP has come out of reset. This signal is synchronous to coreclkout_hip. When port bifurcation is used, there is one such signal for each Avalon® -ST interface. The signals are differentiated by the prefixes pn. This is a per-port signal.
ninit_done Input Asynchronous EP/RP A "1" on this active-low signal indicates that the FPGA device is not yet fully configured. A "0" indicates the device has been configured and is in normal operating mode.