P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 12/13/2021

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Document Table of Contents

A.3.10. Correctable Internal Error Mask Register (Offset 0x40)

This register controls which errors are forwarded as internal correctable errors.

Table 149.  Correctable Internal Error Mask Register
Bits Register Description Default Value Access
[31:12] Reserved 0x0 RO
[11] Mask for Correctable ECC error status for Config RAM. 0x1 RWS
[10:7] Reserved 0x0 RWS
[6] Mask for Correctable Internal Error reported by the FPGA. 0x1 RWS
[5] Mask for Configuration Error detected in CvP mode. This bit is only available for Port 0 ( PCIe* Gen4 x16), but not for the other Ports. 0x1 RWS
[4] Reserved 0x1 RWS
[3:0] Reserved 0x0 RWS