P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 12/13/2021

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Document Table of Contents Second-Level Debug Tools

Use the following debug tools for second-level debug of any issue observed on the PCI Express link when using P-Tile:

Using the Configuration Output Interface

Using the Error Interface

  • Refer to the section Error Interface for details on this interface and the address map.

Using the Configuration Intercept Interface

Using the TX/RX Flow Control Interfaces

Using the Hard IP Reconfiguration Interface

Using the PHY Reconfiguration Interface