P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 12/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.2.2.1. VirtIO Supported Features List

  • VirtIO devices are implemented as PCI Express devices.
  • Support 8 PFs and 2K (up to 2047) VFs VirtIO capability structure for each EP.
  • Configuration Intercept Interface in the P-Tile IP for PCIe (EP mode only) is provided for VirtIO transport.
  • Five VirtIO device configuration structures are supported:
    • Common configuration
    • Notifications
    • ISR Status
    • Device-specific configuration (optional)
    • PCI configuration access
  • Location of each structure is specified using a vendor-specific PCI capability located in the PCI configuration space of the device.
  • VirtIO capability structure uses little-endian format.
  • All fields of the VirtIO capability structure are read-only for the driver by default.
  • Supports x16 and x8 cores.
  • MSI is not supported with VirtIO.