P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 12/13/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

A. Egress Control Vector (Offset 0x8)

Table 138.  Egress Control Vector
Bits Register Description Default Value Access
[31:0] Egress Control Vector 0x0 RO