P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 12/13/2021

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Document Table of Contents

E.4. Configure the Avery BFM and Update the Simulation Script

Configure the Avery BFM

In this example, the Avery BFM in the apci_top_rc.v file is configured to support Gen4 x16 simulations as shown below:

`define APCI_NUM_LANES 16 // default: 16 lanes

rc.cfg_info.speed_sup = 4 // default: Gen4 speed

Dumping waveforms into the VPD file is also enabled in apci_top_rc.v (see $vcdpluson() task). If you want to disable it, comment out +define+APCI_DUMP_VPD in the avery_files_vcs.f file.

Update the Simulation Script

Before you compile/simulate the design, update the <example design folder>/pcie_ed_tb/pcie_ed_tb/sim/synopsys/vcs/vcs_setup.sh script file to include the Avery file and debug options (shown in bold) for the VCS command:

  • vcs -lca -f avery_files_vcs.f -debug_pp -timescale=1ps/1ps …
Note: The QUARTUS_INSTALL_DIR in vcs_setup.sh points to the Quartus installation directory. If you are using the vcs_setup.sh provided in the downloaded .zip file, you need to update the path per your local Quartus installation.

For details, refer to apci_top_rc.v, avery_vcs_files.f, and vcs_setup.sh provided in the downloaded .zip file.