P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 12/13/2021

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Document Table of Contents SR-IOV Supported Features List

Table 12.  SR-IOV Supported Features
Feature Support

Supported in x16/x8 controller EP mode.

Not supported in RP mode (x4).


Supported in PFs only. Not supported in VFs.

No Per Vector Masking (PVM). If you need PVM, you must use MSI-X.

Note: When SR-IOV is enabled, either MSI or MSI-X must be enabled.

Supported by all PFs.

For SR-IOV, PFs and VFs are always MSI-X capable.

Note: VFs share a common Table Size. VF Table BIR/Offset and PBA BIR/Offset are fixed at compile time.
Note: When SR-IOV is enabled, either MSI or MSI-X must be enabled.
Function Level Reset (FLR)

Supported by all PFs/VFs.

Required for all SR-IOV functions.

Extended Tags

Supported by all PFs/VFs. The Extended Tags feature allows the TLP Tag field to be 8-bit, thus allowing the support of 256 tags.

Note that the application is restricted to a max of 256 outstanding tags, at any given time, for all functions combined.

The application logic is responsible for implementing the tag generation/tracking functions.

This feature is reflected in the Extended Tag Field Supported in the Device Capabilities register. By default, this field is set to 1 in every physical function enabled in the Intel FPGA P-Tile IP for PCI Express.

10-bit Tags Supported by all PFs/VFs. Refer to Tag Allocation for more details.

PFs are always AER capable. No AER implemented for VFs.

Active-State Power Management (ASPM) Optionality Compliance

Supported by all PFs/VFs.

Only used to indicate ASPM is not supported.

Atomic Ops

Requester capability is supported by all PFs/VFs.

Completer capability is supported.

Compare and Swap (CAS) AtomicOps are also supported. They can handle up to 128-bit operands.

Internal Error Reporting Supported by all PFs (because all PFs are AER capable). No support for VFs (because VFs do not support AER).
TLP Processing Hints

2-bit Processing Hint and 8-bit Steering Tag are supported by all PFs/VFs. TPH Prefixes are not supported.

You can optionally choose to enable the TPH Requestor capability. However, the IP is always TPH Completer capable.

ID-Based ordering

Supported by all PFs/VFs.

However, the IP core does NOT perform the reordering. The Application Layer must do this.

The IP core only provides the IDO Request & Completion Enable bits in the Device Control 2 register. This gives the application permission to set the Attr bits in Requests and Completions that it transmits.

Note: Reordering capability on the RX side may be limited by your bypass queue. On the TX side, the IP core does not set the IDO bits on internally generated TLPs.
Relaxed Ordering

Implemented on the RX side. This feature is always active.

On the TX side, reordering is done by the application.

Alternative Routing ID Interpretation (ARI)

EP (PFs/VFs) is always ARI capable. This is a device-level option (all lanes or none will support ARI).

In addition, RP will always be ARI capable (ARI Forwarding Supported bit is always 1).

Address Translation Service (ATS) Supported by all EP PFs/VFs.
Page Request Service Interface (PRI) Supported by all EP PFs/VFs.
User Extensions (Customer VSEC) Supported by all PFs/VFs.
Gen3 Receiver Impedance (3.0 ECN) Supported
Device Serial Number Supported
Completion Timeout Ranges (Device Capabilities 2) All ranges are supported.

Data Link Layer Active Reporting Capability (Link Capabilities)

This capability is always supported in RP mode, but not in EP mode.
Surprise Down Error Reporting Capability (Link Capabilities) Supported
PM-PCI Power Management Only D0/D3 states are supported.
ASPM (L0s/L1) Not supported
Process Address Space ID (PASID) Supported
TLP prefix Supported, mainly for PASID
Latency Tolerance Reporting (LTR) Supported (only for PASID)
Access Control Services Supported