P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide
A newer version of this document is available. Customers should click here to go to the newest version.
Visible to Intel only — GUID: eyn1540248671330
Ixiasoft
Visible to Intel only — GUID: eyn1540248671330
Ixiasoft
A.3.4. JTAG Silicon ID (Offset 0x0C - 0x18)
This read-only register returns the JTAG Silicon ID. Intel programming software uses this JTAG ID to ensure that is is using the correct SRM Object File (*.sof).
These registers are only good for Port 0 ( PCIe* Gen4 x16). They are blocked for the other Ports.
Bits | Register Description | Default Value7 | Access |
---|---|---|---|
[127:96] | JTAG Silicon ID DW3 | Unique ID | RO |
[95:64] | JTAG Silicon ID DW2 | Unique ID | RO |
[63:32] | JTAG Silicon ID DW1 | Unique ID | RO |
[31:0] | JTAG Silicon ID DW0 | Unique ID | RO |