1.1. Functional Description for the Programmed Input/Output (PIO) Design Example
The PIO design example performs memory
transfers from a host processor to a target device.
In this example, the host
processor requests single-dword MemRd and MemWr TLPs.
The P-Tile PIO design example automatically creates the files necessary to
simulate and compile in the
Quartus® Prime software. You can
download the compiled design to an
Development Kit. The design example covers a wide range of parameters. However, it does not
cover all possible parameterizations of the P-Tile Hard IP for PCIe.
includes the following components:
P-Tile Avalon-ST Hard
(DUT) with the parameters you specified. This component drives TLP data received to the PIO
The PIO Application (APPS)
performs the necessary translation between the PCI Express TLPs and simple
and reads to the on-chip memory.
on-chip memory (MEM)
The simulation testbench instantiates the P-Tile PIO design example and a
Root Port BFM to interface with the target Endpoint.
Figure 1. Block Diagram for the Platform Designer PIO
Design Example Simulation Testbench
The test program writes
reads back data from the
in the on-chip memory. It compares
data read to the expected result. The test reports, "Simulation stopped due
to successful completion" if no errors occur.
Avalon®-ST design example
supports the following configurations:
Gen4 x16 Endpoint
Gen3 x16 Endpoint
Figure 2. Platform Designer System Contents for
Avalon®-ST PCI Express PIO Design
Example The Platform Designer generates this design
for up to
Note: For the 19.1.1 release of the
Quartus® Prime software, the P-Tile PIO design example only supports
simulation and compilation. It does not support .sof file
generation and hardware testing.
1.2. Serial Data Signals
This differential, serial interface is the physical link between
a Root Port and an Endpoint.
P-Tile PCIe IP Core supports
or 16 lanes. Each lane includes a TX and RX differential pair. Data is striped across
all available lanes.
Table 1. Serial
SignalsIn the following table <n> is the number of lanes.
Transmit output. These signals are the serial outputs
of lanes <n>-1–0.
Receive input. These signals are the serial inputs of
Refer to Pin-out Files for Intel Devices for
pin-out tables for all Intel devices in .pdf,
.txt, and .xls
There are no control registers for the PIO design example. The PCI Express Base Specification
defines a comprehensive set of configuration, control, and status registers to control and
debug the design example.
2. Quick Start Guide
Quartus® Prime software,
you can generate a
programmed I/O (PIO) design example for the
Intel® FPGA P-Tile
Hard IP for
IP core. The generated design
example reflects the parameters that you specify. The PIO example transfers data from a host
processor to a target device. It is appropriate for low-bandwidth applications. This design
example automatically creates the files necessary to simulate and compile in the
software. You can download the compiled design to
Development Board. To download to custom hardware, update the
Quartus® Prime Settings File (.qsf) with the
correct pin assignments .
Figure 3. Development Steps for the Design Example
2.1. Directory Structure
Figure 4. Directory Structure for the Generated Design Example
2.2. Generating the Design Example
Figure 5. Procedure
Quartus® Prime Pro Edition
software, create a new project (File > New Project Wizard).
Specify the Directory,
Name, and Top-Level
For Project Type,
accept the default value, Empty project.
For Add Files click
For Family, Device & Board
Settings under Family,
and the Target Device for your design.
In the IP Catalog locate and add the Intel
Avalon®-STHard IP for
In the New IP Variant
dialog box, specify a name for your IP. Click Create.
On the Top-Level
Settings tabs, specify the parameters for your IP
On the Example Designs
tab, make the following selections:
For Available Example
For Example Design
Files, turn on the Simulation and Synthesis options. If you do not need these simulation
or synthesis files, leaving the corresponding option(s) turned off
significantly reduces the example design generation time.
For Generated HDL
Format, only Verilog is available in the current
Select Generate Example
Design to create a design example that you can simulate and
download to hardware. If you select one of the
development boards, the device on that board overwrites the device previously
selected in the
Quartus® Prime project if the
devices are different. When the prompt asks you to specify the directory for
your example design, you can accept the default directory, ./intel_pcie_ptile_ast_0_example_design,
or choose another directory.
Figure 6. Example Design Tab
Click Finish. You may
save your .ip file when prompted, but it
is not required to be able to use the example design.
Open the example design project.
Compile the example design project to generate the .sof file for the complete example design. This
file is what you download to a board to perform hardware verification.
Close your example design project.
2.3. Simulating the Design Example
Figure 7. Procedure
Change to the testbench simulation directory, pcie_example_design_tb.
Run the simulation script for the simulator of your choice. Refer to the