FPGA AI Suite: Design Examples User Guide

ID 848957
Date 4/30/2025
Public
Document Table of Contents

21.1.1. [SOC] Quartus® Prime Build Flow

All FPGA AI Suite design examples are built by running the dla_build_example_design.py command.

This command generates an FPGA AI Suite IP from the provided architecture file, creates an Quartus® Prime build directory, builds the Quartus® Prime project, and produces a bitstream.

For more information about this command, refer to The dla_build_example_design.py Command

You can build the following SoC design example variants with the dla_build_example_design.py command:
Table 12.  SoC Design Example Variant

Design Example Variant Identifier

Description

Layout Transform
agx5_soc_m2m Builds a memory-to-memory (M2M) design for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit External demonstration transform as described in [SOC] The Layout Transform IP as an Application-Specific Block.
agx5_soc_s2m Builds a memory-to-memory (M2M) design for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit External demonstration transform as described in [SOC] The Layout Transform IP as an Application-Specific Block.
agx7_soc_m2m Builds a memory-to-memory (M2M) design for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit External demonstration transform as described in [SOC] The Layout Transform IP as an Application-Specific Block.
agx7_soc_s2m Builds a streaming-to-memory (S2M) design for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit FPGA AI Suite IP input layout transform must be enabled in the architecture file.

For information about the input layout transform, refer to "Input Layout Transform Hardware" in FPGA AI Suite IP Reference Manual .

a10_soc_m2m Builds a memory-to-memory (M2M) design for the Arria® 10 SX SoC FPGA Development Kit External demonstration transform as described in [SOC] The Layout Transform IP as an Application-Specific Block.
a10_soc_s2m Builds a streaming-to-memory (S2M) design for the Arria® 10 SX SoC FPGA Development Kit External demonstration transform as described in [SOC] The Layout Transform IP as an Application-Specific Block.
An example of building the Arria® 10 S2M variant with the A10_Performance architecture is as follows:
dla_build_example_design.py build \
   --output-dir $COREDLA_WORK/a10_perf_bitstream \
   -n 1 \
   a10_soc_s2m \
   $COREDLA_ROOT/example_architectures/A10_Performance.arch

After the design is built, the output products (.sof or .rbf files) must be combined with the SoC Linux system in order to be used. This is done in one of the steps in the create_hps_image.sh script.

For Agilex™ 5 and Agilex™ 7, the .sof file is combined with a u-boot-spl-dtb.hex file to create either a bootable .sof file or a .jic file that can program the flash memory.

For Arria® 10, the .rbf files are added to the .wic image so that the FPGA device can be programmed from the SD card.

If you attempt to reprogram a running Linux system with a new .sof file, the Linux system crashes and the reprogramming results in an unpredictable outcome.

The FPGA device is programmed by booting the Linux system on the SoC via the SD card (for Arria® 10) or by programming over JTAG (for Agilex™ 5 and Agilex™ 7), which then boots the Linux system from the SD card. For details about creating a functional solution by combining the build .rbf files with the SD card image or by creating the bootable .sof or .jic files, refer to [SOC] Building the Bootable SD Card Image (.wic).