FPGA AI Suite: Design Examples User Guide

ID 848957
Date 4/30/2025
Public
Document Table of Contents

13. [HL-NO-DDR] Quartus® Prime System Console

This design example requires user interaction on the host system through Quartus® Prime System Console. For more information about the Quartus® Prime System Console, refer to "Analyzing and Debugging Designs with System Console" in Quartus® Prime Pro Edition User Guide: Debug Tools .

The system console user interface communicates over JTAG to a JTAG to Avalon-MM host IP that enables the following functions:
You can find an example Quartus® Prime System Console Tcl script in the following location:
$COREDLA_ROOT/runtime/streaming/ed0_streaming_example/system_console_script.tcl