8.2.4. [OFS-PCIE] Compiling the OFS for PCIe* Attach Design Example
To build example design bitstreams, you must have a license that permits bitstream generation for the IP, and have the correct version of Quartus® Prime software installed. Use the dla_build_example_design.py utility to create a bitstream.
For details about this command, the steps it performs, and advanced command options, refer to The dla_build_example_design.py Command and to the FPGA AI Suite Getting Started Guide .
https://github.com/OFS/ofs-agx7-pcie-attach/releases/The FPGA AI Suite OFS for PCIe* Attach design example is based on the OFS 2024.3 release of the reference shells.
The dla_build_example_design.py utility generates a wrapper that wraps one or more FPGA AI Suite IP instances along with adapters required to connect to the OFS slim FIM.
Get an estimate of the FPGA resource required for a single FPGA AI Suite IP instance by using the --fanalyze-area option of the dla_compiler. Use the single instance values to determine the resources required for the number of instances that you want. For more details, see the --fanalyze-area option description in FPGA AI Suite Compiler Reference Manual .
cd $COREDLA_WORK dla_build_example_design.py build \ --output-dir build_generic_2inst \ --seed 1 \ --num-instances 2 agx7_iseries_ofs_pcie \ $COREDLA_ROOT/example_architectures/AGX7_Generic.arch \
This command generates a green bitstream (GBS) file called AGX7_Generic.gbs that can be found in the $COREDLA_WORK/build_generics_2inst/ folder.