FPGA AI Suite: Design Examples User Guide

ID 848957
Date 4/30/2025
Public
Document Table of Contents

8.2.4. [OFS-PCIE] Compiling the OFS for PCIe* Attach Design Example

To build example design bitstreams, you must have a license that permits bitstream generation for the IP, and have the correct version of Quartus® Prime software installed. Use the dla_build_example_design.py utility to create a bitstream.

For details about this command, the steps it performs, and advanced command options, refer to The dla_build_example_design.py Command and to the FPGA AI Suite Getting Started Guide .

Before running the dla_build_example_design.py utility, ensure that the OPAE_PLATFORM_ROOT environment variable points to your OFS FPGA interface manager (FIM) pr_build_template directory. If you do not want to compile your own FIM, you can get prebuilt OFS FIM binaries for boards supported by the Agilex™ 7 OFS for PCIe* Attach reference shells on GitHub at the following URL:
https://github.com/OFS/ofs-agx7-pcie-attach/releases/
The FPGA AI Suite OFS for PCIe* Attach design example is based on the OFS 2024.3 release of the reference shells.

The dla_build_example_design.py utility generates a wrapper that wraps one or more FPGA AI Suite IP instances along with adapters required to connect to the OFS slim FIM.

Important: The OFS FIM uses FPGA resources as well as the FPGA AI Suite IP instances. Keep the FPGA resource limitations in mind when deciding on how many FPGA AI Suite IP instances to use.

Get an estimate of the FPGA resource required for a single FPGA AI Suite IP instance by using the --fanalyze-area option of the dla_compiler. Use the single instance values to determine the resources required for the number of instances that you want. For more details, see the --fanalyze-area option description in FPGA AI Suite Compiler Reference Manual .

To generate an FPGA bitstream for the OFS for PCIe* Attach design example for the Agilex™ 7 FPGA I-Series Development Kit with two FPGA AI Suite IP instances, run the following commands:
cd $COREDLA_WORK

dla_build_example_design.py build \
  --output-dir build_generic_2inst \
  --seed 1 \
  --num-instances 2
  agx7_iseries_ofs_pcie \
  $COREDLA_ROOT/example_architectures/AGX7_Generic.arch \

This command generates a green bitstream (GBS) file called AGX7_Generic.gbs that can be found in the $COREDLA_WORK/build_generics_2inst/ folder.