FPGA AI Suite: Design Examples User Guide

ID 848957
Date 4/30/2025
Public
Document Table of Contents

15. [HL-NO-DDR] Updating MIF Files

The design example build process uses *.mif files to initialize the on-chip M2Ks. The M20Ks store filters, bias, and configuration data on-chip rather than in external memory. The DDR-free flow allows inference of different graphs using the “update_mif” feature of Quartus® Prime software without needing to recompile the bitstream. You must guarantee that the filter, bias, and configuration cache depth are large enough to hold the new graph parameters and FPGA AI Suite IP configuration.

After a design example is compiled, you can update the contents of the M20Ks through the Quartus® Prime tools. The commands regenerate the top.sof bitstream file that needs to be reprogrammed on the device.

The Quartus® Prime tools do not change the architecture of the FPGA AI Suite IP,. The update only the contents of the on-chip M20Ks that store the graph information and the FPGA AI Suite IP configuration.

To update the contents of the M20K on-chip memory:

  1. Recompile the .mif files for the new graph as described in [HL-NO-DDR] Running the Hostless DDR-Free Design Example.
  2. Replace the .mif files under “ <path/to/build/dir>/coredla_ip/intel_ai_ip/verilog/.” with the files that were created in the previous step.
  3. Run the following commands from “ <path/to/build/dir>/hw/”:
    quartus_cdb top -c top --update_mif
    
    quartus_asm --read_settings_files=on --write_settings_files=off top -c top