FPGA AI Suite: Design Examples User Guide

ID 848957
Date 4/30/2025
Public
Document Table of Contents

B. FPGA AI Suite Example Designs User Guide Revision History

Document Version FPGA AI Suite Version Changes
2025.04.30 2025.1
  • Updated and revised some sections under Design Example Software Components:
    • Added OpenVINO™ FPGA Runtime Overview
    • Added FPGA AI Suite Custom Platform
    • Added FPGA AI Suite Runtime MMD API
    • Removed Software Interface to the BSP
    • Added Board Support Package (BSP) Overview
    • Added Terasic* DE10-Agilex Development Board BSP Example
    • Added Agilex™ 7 PCIe Attach OFS-based BSP Example
2025.04.23 2025.1
  • Made various updates to support the changes to the design example utility (dla_build_example_design.py).
    The following new topics were added:
    • FPGA AI Suite Design Example Utility
    • The dla_build_example_design.py Command
    • Listing Available FPGA AI SuiteDesign Examples
    • Building FPGA AI Suite Design Examples
    • Staging FPGA AI Suite Design Example Builds
    • WSL 2 FPGA AI Suite Design Example Builds
    The following topics were removed:
    • [PCIE] Build Script
    • [PCIE] Build Script Options
    • [PCIE] Script Flow
    The following topics were changed:
    • [OFS-PCIE} Compiling the OFS for PCIe Attach Design Example
    • [HL-NO-DDR] Running the Hostless DDR-Free Design Example
    • [HL-JTAG] Building an FPGA Bitstream for the JTAG Design Examples
    • [SOC} Quartus Prime Build Flow
    • [SOC] Build Script Options
  • [SOC] Added information for the Agilex™ 5 SoC design example, including the following new topics:
    • Preparing the Agilex™ 5 FPGA E-Series 065B Modular Development Kit
    • Confirming the Agilex™ 5 FPGA E-Series 065B Modular Development Kit Board Setup
    • Programming the Agilex™ 5 FPGA Device with the JTAG Indirect Configuration (.jic) File
    • Programming the Agilex™ 5 FPGA Device with the SRAM Object File (.sof)
    • Connecting the Agilex™ 5 FPGA E-Series 065B Modular Development Kit to the Host Development System
  • [SOC] Revised some steps for the Agilex™ 7 SoC design example.
  • [HL-NO-DDR] Updated some Quartus® Prime System Console script commands.
  • [HL-NO-DDR] Added [HL-NO-DDR] Quartus® Prime System Console Script Options
  • [HL-NO-DDR] Removed [HL-NO-DDR] Quartus Prime System Console Performance Script
  • [HL-NO-DDR] Added [HL-NO-DDR] Measuring Performance
  • Design example support for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit has been replaced with support for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit.
2025.04.22 2024.3
  • Fixed a typo in the command found in Building an FPGA Bitstream for the JTAG Design Examples.
2025.03.28 2024.3 Initial release.
This initial release merges the content from the following publications: The revision histories of these guides is included here for completeness.
This initial release adds information about the following design examples:
  • JTAG Design Example
  • DDR-Free Hostless Design Example
  • OFS for PCIe* Attach Design Example