2.3. About the Hostless DDR-Free Design Example
The FPGA AI Suite provides a design example to demonstrate hostless and DDR-free operation of the FPGA AI Suite IP. Graph filters, bias, and FPGA AI Suite IP configurations are stored in on-chip memory on the FPGA device instead of DDR memory on the board.
The DDR-free design example demonstrates how FPGA AI Suite supports the following features:
- DDR-free operation
- Hostless operation (that is, running on the devices without the FPGA AI Suite runtime)
- Streaming of input features
- Streaming of inference results
The DDR-Free design example is implemented with the following components:
- FPGA AI Suite IP
- Agilex™ 7 FPGA I-Series Development Kit ES2 (DK-DEV-AGI027RBES)
- Sample hardware and software systems that illustrate the use of these components
For more details about DDR-free operation, refer to DDR-Free Operation in the FPGA AI Suite IP Reference Manual .
The design example build scripts in [PCIE] Building the FPGA AI Suite Runtime let you choose from a variety of architecture files and build your own bitstreams, provided that you have a license permitting bitstream generation.
This design is provided with the FPGA AI Suite as an example showing how to incorporate the FPGA AI Suite IP into a DDR-Free design. This design is not intended for unaltered use in production scenarios. Any potential production application that uses portions of this design example must be reviewed for both robustness and security.