GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 817713
Date 5/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example 2. Quick Start Guide 3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example x
1.1. Programmed Input/Output Design Example 1.2. Programmed Input/Output Design Example Functional Description
1.2. Programmed Input/Output Design Example Functional Description x
1.2.1. GTS AXI Streaming IP—Design Under Test (DUT) 1.2.2. PIO Application 1.2.3. On-Chip Memory (MEM) 1.2.4. GTS System PLL Clocks Intel® FPGA IP 1.2.5. GTS Reset Sequencer Intel® FPGA IP 1.2.6. Reset Release Intel® FPGA IP
1.2.2. PIO Application x
1.2.2.1. Scheduler 1.2.2.2. Read Write Module 1.2.2.3. Avalon® Memory-Mapped Interface 1.2.2.4. Completion Module 1.2.2.5. Width Adapter 1.2.2.6. TX Credit Initialization 1.2.2.7. AXI to Avalon® Streaming Interface Adapter
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Design Example Simulation Testbench 2.5. Compiling the Design Example
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulation using VCS* 2.3.2. Steps to Run Simulation using VCS* MX 2.3.3. Steps to Run Simulation using QuestaSim* Working Directory Instructions
2.3.1. Steps to Run Simulation using VCS* x
2.3.1.1. Running VCS* Simulation in Interactive Mode
2.3.2. Steps to Run Simulation using VCS* MX x
2.3.2.1. Running VCS* MX Simulation in Interactive Mode
2.4. Design Example Simulation Testbench x
2.4.1. Test Driver Module 2.4.2. PIO Design Example Testbench
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example
2. Quick Start Guide
3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

2.3.3. Steps to Run Simulation using QuestaSim*

Working Directory

<example_design>/pcie_ed_tb/pcie_ed_tb/sim/mentor/

Instructions

  1. Invoke the QuestaSim* simulator. For Linux environment, run the following command to invoke the QuestaSim* simulator.
    vsim &
  2. Run the following command in the QuestaSim* console window: 
    do msim_setup.tcl
  3. If you are using Windows environment, run the following command in the QuestaSim* console window. Skip this step if you are using Linux environment.
    set TOP_LEVEL_NAME "pcie_ed_tb.pcie_ed_tb"
  4. Run the command below in the QuestaSim* console window to enable FASTSIM mode. Skip this step if the FASTSIM mode is not required.
    set USER_DEFINED_COMPILE_OPTIONS “+define +IP7521SERDES_UX_SIMSPEED"
  5. Run the following command in the QuestaSim* console window to compile the design: 
    ld
run -all
  6. A successful simulation ends with the following message in the simulation.log file that was generated.
    "Simulation stopped due to successful completion!"
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