GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 817713
Date 5/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example 2. Quick Start Guide 3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example x
1.1. Programmed Input/Output Design Example 1.2. Programmed Input/Output Design Example Functional Description
1.2. Programmed Input/Output Design Example Functional Description x
1.2.1. GTS AXI Streaming IP—Design Under Test (DUT) 1.2.2. PIO Application 1.2.3. On-Chip Memory (MEM) 1.2.4. GTS System PLL Clocks Intel® FPGA IP 1.2.5. GTS Reset Sequencer Intel® FPGA IP 1.2.6. Reset Release Intel® FPGA IP
1.2.2. PIO Application x
1.2.2.1. Scheduler 1.2.2.2. Read Write Module 1.2.2.3. Avalon® Memory-Mapped Interface 1.2.2.4. Completion Module 1.2.2.5. Width Adapter 1.2.2.6. TX Credit Initialization 1.2.2.7. AXI to Avalon® Streaming Interface Adapter
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Design Example Simulation Testbench 2.5. Compiling the Design Example
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulation using VCS* 2.3.2. Steps to Run Simulation using VCS* MX 2.3.3. Steps to Run Simulation using QuestaSim*
2.3.1. Steps to Run Simulation using VCS* x
2.3.1.1. Running VCS* Simulation in Interactive Mode
2.3.2. Steps to Run Simulation using VCS* MX x
2.3.2.1. Running VCS* MX Simulation in Interactive Mode
2.4. Design Example Simulation Testbench x
2.4.1. Test Driver Module 2.4.2. PIO Design Example Testbench
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example
2. Quick Start Guide
3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example

Updated for:
Intel® Quartus® Prime Design Suite 24.1
IP Version 4.0.0

GTS AXI Streaming Intel® FPGA IP for PCI Express* design example is a simple design to demonstrate the establishment of the PCI Express* connectivity of Agilex™ 5 FPGA in Quartus® Prime software. The PCIe* system host CPU uses Programmed Input/Output (PIO) transactions to access memory map locations in the design example through the PCIe* link. The Programmed Input/ Output (PIO) application block is needed to handle the translation from PCIe* TLP to Avalon® memory-mapped interface protocol of the on-chip memory.

Attention:
  1. Any occurrence of GTS AXI Streaming IP throughout this document shall constitute a reference to the GTS AXI Streaming Intel® FPGA IP for PCI Express* .
  2. Any occurrence of PCIe* Gen4 or Gen4 throughout this document shall constitute a reference to the PCIe* 4.0.
Table 1.   GTS AXI Streaming Intel® FPGA IP for PCI Express*
Design Example Hard IP Mode Simulation Hardware

PIO

Gen4x4 256-bit Endpoint

Supports VCS* , VCS* MX, QuestaSim* , Questa* Intel® FPGA Edition simulators.

No Support
Important:
  1. Design examples only support the default settings in the parameter editor of the GTS AXI Streaming IP in the Quartus® Prime software.
  2. Design examples do not support the 10-bit tag completer feature. Running the design example on the host machine enforces a 10-bit tag at PCIe* Gen4 and can cause completion timeout or system crashes.
  3. Design example hardware support may be added in a future version of Quartus® Prime software along with the Agilex™ 5 FPGA development kit availability.

Section Content
Programmed Input/Output Design Example
Programmed Input/Output Design Example Functional Description

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