GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 817713
Date 5/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example 2. Quick Start Guide 3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example x
1.1. Programmed Input/Output Design Example 1.2. Programmed Input/Output Design Example Functional Description
1.2. Programmed Input/Output Design Example Functional Description x
1.2.1. GTS AXI Streaming IP—Design Under Test (DUT) 1.2.2. PIO Application 1.2.3. On-Chip Memory (MEM) 1.2.4. GTS System PLL Clocks Intel® FPGA IP 1.2.5. GTS Reset Sequencer Intel® FPGA IP 1.2.6. Reset Release Intel® FPGA IP
1.2.2. PIO Application x
1.2.2.1. Scheduler 1.2.2.2. Read Write Module 1.2.2.3. Avalon® Memory-Mapped Interface 1.2.2.4. Completion Module 1.2.2.5. Width Adapter 1.2.2.6. TX Credit Initialization 1.2.2.7. AXI to Avalon® Streaming Interface Adapter
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Design Example Simulation Testbench 2.5. Compiling the Design Example
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulation using VCS* 2.3.2. Steps to Run Simulation using VCS* MX 2.3.3. Steps to Run Simulation using QuestaSim*
2.3.1. Steps to Run Simulation using VCS* x
2.3.1.1. Running VCS* Simulation in Interactive Mode
2.3.2. Steps to Run Simulation using VCS* MX x
2.3.2.1. Running VCS* MX Simulation in Interactive Mode
2.4. Design Example Simulation Testbench x
2.4.1. Test Driver Module 2.4.2. PIO Design Example Testbench
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example
2. Quick Start Guide
3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

2.2. Generating the Design Example

Figure 5. Procedure to Generate Design Example
Figure 6. Example Designs Tab
  1. In the Quartus® Prime Pro Edition software, create a new project (File ➤ New Project Wizard).
  2. Specify the Directory, Name and Top-Level Entity.
  3. For Project Type, accept the default value, Empty project. Click Next.
  4. For Add Files click Next.
  5. For Family, Device & Board Settings under Family, select Agilex 5.
  6. Select the Target Device for your design.
  7. Click Finish.
  8. In the IP Catalog, locate and add the GTS AXI Streaming Intel FPGA IP for PCI Express.
  9. In the New IP Variant dialog box, specify a name for your IP. Click Create.
  10. On the Top-Level Settings tabs, specify the parameters for your IP variation.
    Note: This design example only supports the Gen4 x4 with default settings in the parameter editor of the GTS AXI Streaming Intel® FPGA IP for PCI Express* .
  11. On the Example Designs tab, make the following selections:
    • For Example Design Files, turn on the Simulation and Synthesis options. If you do not need these simulation or synthesis files, leaving the corresponding option(s) turned off significantly reduces the design example generation time.
    • For Generated HDL Format, both Verilog and VHDL are supported in the current release.
    • For Currently Selected Example Design, only PIO is supported in this release.
  12. Select Generate Example Design to create a design example that you can simulate. When the prompt asks you to specify the directory for your design example, you can accept the default directory, /intel_pcie_gts_0_example_design , or choose another directory.
  13. Click Finish. You may save your .ip file when prompted, but it is not required to be able to use the design example.
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