GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 817713
Date 5/09/2024
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Document Table of Contents
Document Table of Contents x
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example 2. Quick Start Guide 3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example x
1.1. Programmed Input/Output Design Example 1.2. Programmed Input/Output Design Example Functional Description
1.2. Programmed Input/Output Design Example Functional Description x
1.2.1. GTS AXI Streaming IP—Design Under Test (DUT) 1.2.2. PIO Application 1.2.3. On-Chip Memory (MEM) 1.2.4. GTS System PLL Clocks Intel® FPGA IP 1.2.5. GTS Reset Sequencer Intel® FPGA IP 1.2.6. Reset Release Intel® FPGA IP
1.2.2. PIO Application x
1.2.2.1. Scheduler 1.2.2.2. Read Write Module 1.2.2.3. Avalon® Memory-Mapped Interface 1.2.2.4. Completion Module 1.2.2.5. Width Adapter 1.2.2.6. TX Credit Initialization 1.2.2.7. AXI to Avalon® Streaming Interface Adapter
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Design Example Simulation Testbench 2.5. Compiling the Design Example
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulation using VCS* 2.3.2. Steps to Run Simulation using VCS* MX 2.3.3. Steps to Run Simulation using QuestaSim*
2.3.1. Steps to Run Simulation using VCS* x
2.3.1.1. Running VCS* Simulation in Interactive Mode
2.3.2. Steps to Run Simulation using VCS* MX x
2.3.2.1. Running VCS* MX Simulation in Interactive Mode
2.4. Design Example Simulation Testbench x
2.4.1. Test Driver Module 2.4.2. PIO Design Example Testbench
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example
2. Quick Start Guide
3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

1.1. Programmed Input/Output Design Example

The GTS AXI Streaming IP design example serves as a known established working design to verify the PCIe* Gen4 link and functionality on the Agilex™ 5 FPGA board. The GTS AXI Streaming IP runs up to 350 MHz at the user interface with a maximum data width of 256 bits for PCIe* 4.0 x4 link. The clock frequency is supplied from the coreclkout_hip_toapp to axi_st_clk, which is limited to 350 MHz.
The design example consists of 3 main components:
  • Generated GTS AXI Streaming IP as Endpoint Variant (DUT)
  • Programmable I/O Application (PIO)
  • On-Chip Memory (MEM)

The GTS AXI Streaming IP design under test (DUT) is configured as an Endpoint receiving the PIO transactions from the root complex over the PCIe* link and transferring them to the PIO application module. The TLP received in the PIO application module is decoded and converted into Avalon® memory-mapped interface format. Depending on the received instruction, the on-chip memory is the targeted space to store or read data.

The PIO design example automatically creates the required files for simulation and compilation in the Quartus® Prime software. However, it does not cover all possible GTS AXI Streaming IP parameterizations.

Below are the limitations of the design example:
  • There is no support on the back-to-back TLP packets from the host processor.
  • TLP prefix is not used and intended with Single Physical Function (PF).
  • There is no requirement for error message, interrupt or status bit toggling handling.
  • The backpressure mechanism of the DUT is handled through the ready signal. Besides ready, receive (RX) signals can also be backpressured through p0_app_ss_st_rx_tuser_halt. There is also the (transmit) TX credit mechanism of back pressure.
  • Does not include the full features of the GTS AXI Streaming IP.
Figure 1.  PCIe* 4.0 x4 Design Example Variant Block Diagram
Level Two Title