GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
ID
817713
Date
5/09/2024
Public
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1.2.5. GTS Reset Sequencer Intel® FPGA IP
The GTS Reset Sequencer Intel® FPGA IP must be instantiated for each device side that uses transceivers. Based on your design, you must instantiate one or two instances of the IP:
- One GTS Reset Sequencer Intel® FPGA IP instance if your design uses transceivers on one side of the device.
- Two GTS Reset Sequencer Intel® FPGA IP instances if your design uses transceivers on both sides of the device.
For more information, refer to the Implementing the GTS Reset Sequencer Intel® FPGA IP section in the GTS Transceiver PHY User Guide.