GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 817713
Date 5/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example 2. Quick Start Guide 3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example x
1.1. Programmed Input/Output Design Example 1.2. Programmed Input/Output Design Example Functional Description
1.2. Programmed Input/Output Design Example Functional Description x
1.2.1. GTS AXI Streaming IP—Design Under Test (DUT) 1.2.2. PIO Application 1.2.3. On-Chip Memory (MEM) 1.2.4. GTS System PLL Clocks Intel® FPGA IP 1.2.5. GTS Reset Sequencer Intel® FPGA IP 1.2.6. Reset Release Intel® FPGA IP
1.2.2. PIO Application x
1.2.2.1. Scheduler 1.2.2.2. Read Write Module 1.2.2.3. Avalon® Memory-Mapped Interface 1.2.2.4. Completion Module 1.2.2.5. Width Adapter 1.2.2.6. TX Credit Initialization 1.2.2.7. AXI to Avalon® Streaming Interface Adapter
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Design Example Simulation Testbench 2.5. Compiling the Design Example
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulation using VCS* 2.3.2. Steps to Run Simulation using VCS* MX 2.3.3. Steps to Run Simulation using QuestaSim*
2.3.1. Steps to Run Simulation using VCS* x
2.3.1.1. Running VCS* Simulation in Interactive Mode
2.3.2. Steps to Run Simulation using VCS* MX x
2.3.2.1. Running VCS* MX Simulation in Interactive Mode
2.4. Design Example Simulation Testbench x
2.4.1. Test Driver Module 2.4.2. PIO Design Example Testbench
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example
2. Quick Start Guide
3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

2.4. Design Example Simulation Testbench

The simulation testbench instantiates the PIO design example and a Root Port bus functional model (BFM) to interface with the target Endpoint.

The testbench uses a test driver module, altpcietb_bfm_rp_gen4_x16.sv, to initiate the configuration and memory transactions. At startup, the test driver module displays information from the Root Port and Endpoint Configuration Space registers, so that you can correlate to the parameters you specified using the IP parameter editor in the Quartus® Prime software.

The design example and testbench are dynamically generated based on the configuration that you choose for the GTS AXI Streaming IP.

This testbench simulates up to an x4 PCI Express* link using the serial PCI Express* interface.

The following figure presents a high-level view of the PIO design example.

Figure 8. PCIe x4 PIO Design Example Simulation Testbench
The top level of the testbench instantiates the three main modules as listed in the following table:
Table 6.  Simulation Testbench Modules
Module Description Directory Path
altpcietb_bfm_rp_gen4x16.sv Root Port PCIe* * BFM. 
//Directory path 
<project_dir>/intel_pcie_gts_0_example_design/pcie_ed_tb/ip/pcie_ed_tb/ 
dut_pcie_tb_ip/intel_pcie_gts_tbed_<ver>/sim
pcie_ed_dut.ip Endpoint design with the parameters that you specify. 
//Directory path 
<project_dir>/intel_pcie_gts_0_example_design/ip/pcie_ed
pcie_ed_pio0.ip A a target and initiator of transactions for the PIO design example. 
//Directory path 
<project_dir>/intel_pcie_gts_0_example_design/ip/pcie_ed
The testbench also has routines that perform the following tasks:
  • Generates the reference clock for the Endpoint at the required frequency.
  • Provides a PCI Express* reset at start-up.

Section Content
Test Driver Module
PIO Design Example Testbench

Level Two Title