GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 817713
Date 5/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example 2. Quick Start Guide 3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example x
1.1. Programmed Input/Output Design Example 1.2. Programmed Input/Output Design Example Functional Description
1.2. Programmed Input/Output Design Example Functional Description x
1.2.1. GTS AXI Streaming IP—Design Under Test (DUT) 1.2.2. PIO Application 1.2.3. On-Chip Memory (MEM) 1.2.4. GTS System PLL Clocks Intel® FPGA IP 1.2.5. GTS Reset Sequencer Intel® FPGA IP 1.2.6. Reset Release Intel® FPGA IP
1.2.2. PIO Application x
1.2.2.1. Scheduler 1.2.2.2. Read Write Module 1.2.2.3. Avalon® Memory-Mapped Interface 1.2.2.4. Completion Module 1.2.2.5. Width Adapter 1.2.2.6. TX Credit Initialization 1.2.2.7. AXI to Avalon® Streaming Interface Adapter
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Design Example Simulation Testbench 2.5. Compiling the Design Example
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulation using VCS* 2.3.2. Steps to Run Simulation using VCS* MX 2.3.3. Steps to Run Simulation using QuestaSim*
2.3.1. Steps to Run Simulation using VCS* x
2.3.1.1. Running VCS* Simulation in Interactive Mode
2.3.2. Steps to Run Simulation using VCS* MX x
2.3.2.1. Running VCS* MX Simulation in Interactive Mode
2.4. Design Example Simulation Testbench x
2.4.1. Test Driver Module 2.4.2. PIO Design Example Testbench
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example
2. Quick Start Guide
3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

1.2.2. PIO Application

The PIO Application component performs the necessary translation between the PCI Express* TLPs and simple Avalon® memory-mapped interface writes and reads to the on-chip memory. The PIO component interfaces between the AXI Stream interface and Avalon® memory-mapped interface.

It decodes the TLP headers/data and converts it into Avalon® memory-mapped interface compatible instructions. A single write data TLP is converted into a single Avalon® memory-mapped interface write instruction for a write operation. For the read operation, it could be multiple data read back depending on the maximum payload size boundary. It reads and writes in 512-bits and supports contiguous byte enables. These operations are done in the Bursting Avalon® Master module in the PIO Application, which consists of four sub-modules:
  • Scheduler
  • Read Write module
  • Avalon® memory-mapped interface
  • Completion module

Section Content
Scheduler
Read Write Module
Avalon Memory-Mapped Interface
Completion Module
Width Adapter
TX Credit Initialization
AXI to Avalon Streaming Interface Adapter

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