GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
ID
817713
Date
5/09/2024
Public
A newer version of this document is available. Customers should click here to go to the newest version.
1.2. Programmed Input/Output Design Example Functional Description
Figure 2. Platform Designer System Contents for the GTS AXI Streaming IP PIO Design Example ( PCIe* 4.0 x4 Variant)