GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 817713
Date 5/09/2024
Public

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2.3. Simulating the Design Example

Figure 7. Procedure to Simulate the Design Example
  1. Run the simulation script under <example_design> /pcie_ed_tb/pcie_ed_tb/sim/<simulator> directory for the simulator of your choice.
  2. Analyze the results.
FASTSIM mode is supported in the Programmed Input/Output Design Example simulation. In the FASTSIM mode, a simplified PMA abstract model along with strategies for simulation duration reduction are employed to improve the overall simulation time for the GTS AXI Streaming Intel® FPGA IP for PCI Express* . The PMA model has a compile-time switch “IP7521SERDES_UX_SIMSPEED” to use a simplified PMA abstract model. If the switch is not defined by compile environment, then a detailed or existing model is used.