External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 1/13/2025
Public

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4.6.32. ref_clk for External Memory Interfaces (EMIF) IP - LPDDR5

Reference clock used by the EMIF PLL.

Table 168.  Interface: ref_clkInterface type: clock
Port Name Direction Description
ref_clk Input PLL reference clock input.