External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 1/13/2025
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.4. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 DIMM

The interfaces in the External Memory Interfaces (EMIF) IP - DDR5 DIMM each have signals that can be connected in Platform Designer. The following table lists the interfaces and corresponding interface types.

Table 75.  Interfaces for External Memory Interfaces (EMIF) IP - DDR5 DIMM
Interface Name Interface Type Description
s0_axi4_ctrl_ready reset Reset for mainband, from primary I/O bank, indicating the calibration is complete. Only available if mainband is accessed through fabric.
s1_axi4_ctrl_ready reset Reset for mainband, from secondary I/O bank, indicating the calibration is complete. Only available if mainband is accessed through fabric.
s0_axi4_clock_in clock Input user clock for mainband; for MAINBAND_ACCESS_MODE = ASYNC only.
core_init_n reset An input to indicate that core configuration is complete.
s0_axi4 axi4 Mainband AXI4 from fabric to controller, channel 0.
s1_axi4 axi4 Mainband AXI4 from fabric to controller, channel 1.
s0_axi4lite_clock clock Clock for sideband interface (primary I/O bank).
s0_axi4lite_reset_n reset Reset for sideband interface (primary I/O bank).
s0_axi4lite axi4lite Sideband interface (primary I/O bank) that will connect to the IOSSM, through a gearbox in the core.
s1_axi4lite_clock clock Clock for sideband interface (secondary I/O bank).
s1_axi4lite_reset_n reset Reset for sideband interface (secondary I/O bank).
s1_axi4lite axi4lite Sideband interface (secondary I/O bank) that will connect to the IOSSM, through a gearbox in the core.
mem_0 conduit Interface to the memory (channel 0), including all CA pins, DQ pins, and DQS pins.
mem_1 conduit Interface to the memory (channel 1), including all CA pins, DQ pins, and DQS pins.
mem_reset_n conduit Reset pin to the memory. Must always be placed along with channel 0, but shared for entire interface (all channels within one EMIF).
mem_ck_0 conduit Clock pin to the memory (channel 0).
mem_ck_1 conduit Clock pin to the memory (channel 1).
oct_0 conduit On-Chip Termination (OCT) interface, representing RZQ pin (channel 0).
oct_1 conduit On-Chip Termination (OCT) interface, representing RZQ pin (channel 1).
ref_clk clock Reference clock used by the EMIF PLL.