External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 1/13/2025
Public

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4.6.21. mem_1 for External Memory Interfaces (EMIF) IP - LPDDR5

Interface to the memory (channel 1), including all CA pins, DQ pins, and DQS pins.

Table 157.  Interface: mem_1Interface type: conduit
Port Name Direction Description
mem_1_cs Output Chip Select channel 1.
mem_1_ca Output Command/Address Bus channel 1.
mem_1_dq Bidir Data (read/write) channel 1.
mem_1_rdqs_t Bidir Read Data Strobe (true) channel 1.
mem_1_rdqs_c Bidir Read Data Strobe (complement) channel 1.
mem_1_dmi Bidir Data Mask/Data Inversion channel 1.
mem_1_wck_t Output Write Clock (true) channel 1.
mem_1_wck_c Output Write Clock (complement) channel 1.