External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 1/13/2025
Public

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4.5.19. mem_0 for External Memory Interfaces (EMIF) IP - LPDDR4

Interface to the memory (channel 0), including all CA pins, DQ pins, and DQS pins.

Table 122.  Interface: mem_0Interface type: conduit
Port Name Direction Description
mem_0_cs Output Chip Select channel 0.
mem_0_ca Output Command/Address Bus channel 0.
mem_0_cke Output Clock Enable channel 0.
mem_0_dq Bidir Data (read/write) channel 0.
mem_0_dqs_t Bidir Data Strobe (true) channel 0.
mem_0_dqs_c Bidir Data Strobe (complement) channel 0.
mem_0_dmi Bidir Data Mask/Data Inversion channel 0.