External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 1/13/2025
Public

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4.3.13. mem_reset_n_0 for External Memory Interfaces (EMIF) IP - DDR5 Component

Reset pin to the memory (channel 0).

Table 68.  Interface: mem_reset_n_0Interface type: conduit
Port Name Direction Description
mem_0_reset_n Output Asynchronous Reset channel 0.