External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs
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9.2.4.2. LPDDR5 Data Width Mapping
Only fixed byte lanes within the I/O bank can be used as data lanes. The following table lists the supported address and command and data lane placements in an I/O bank.
Controller | Data Width Usage | BL7 [P95:P84] | BL6 [P83:P72] | BL5 [P71:P60] | BL4 [P59:P48] | BL3 [P47:P36] | BL2 [P35:P24] | BL1 [P23:P12] | BL0 [P11:P0] | BL7 [P95:P84] | BL6 [P83:P72] | BL5 [P71:P60] | BL4 [P59:P48] | BL3 [P47:P36] | BL2 [P35:P24] | BL1 [P23:P12] | BL0 [P11:P0] | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Primary | LPDDR5 x16 | GPIO | GPIO | GPIO | GPIO | AC1 P | AC0 P | DQ[1] P | DQ[0] P | |||||||||
Primary & Secondary | LPDDR5 2ch x16 | DQ[1] S | DQS[0] S | AC1 S | AC0 S | AC1 P | AC0 P | DQ[1] P | DQ[0] P | |||||||||
Primary | LPDDR5 x32 | DQ[3] P | DQ[2] P | GPIO | GPIO | AC1 P | AC0 P | DQ[1] P | DQ[0] P | |||||||||
Primary & Secondary | LP DDR5 4ch x16 | DQ[1] S | DQ[0] S | AC1 S | AC0 S | AC1 P | AC0 P | DQ[1] P | DQ[0] P | DQ[1] S | DQ[0] S | AC1 S | AC0 S | AC1 P | AC0 P | DQ[1] P | DQ[0] P | |
Note:
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Refer to the Pin Options for LPDDR5 1ch x32 figure in the LPDDR5 Component Options topic for information on the T-Line routing requirement for address and command pins.