External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 1/13/2025
Public

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4.6.22. mem_ck_1 for External Memory Interfaces (EMIF) IP - LPDDR5

Clock pin to the memory (channel 1).

Table 158.  Interface: mem_ck_1Interface type: conduit
Port Name Direction Description
mem_1_ck_t Output CK Clock (true) channel 1.
mem_1_ck_c Output CK Clock (complement) channel 1.