External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 1/13/2025
Public

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4.5.27. mem_reset_n for External Memory Interfaces (EMIF) IP - LPDDR4

Reset pin to the memory. Must always be placed along with channel 0, but shared for entire interface (all channels within one EMIF).

Table 130.  Interface: mem_reset_nInterface type: conduit
Port Name Direction Description
mem_0_reset_n Output Asynchronous Reset channel 0.