External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 1/13/2025
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6.3.2.1.3. Maximum Number of Interfaces

The maximum number of interfaces supported for a given memory protocol varies, depending on the FPGA in use.

Unless otherwise noted, the calculation for the maximum number of interfaces is based on independent interfaces where the address or command pins are not shared.

Note: You may need to share PLL clock outputs depending on your clock network usage.

Timing closure depends on device resource and routing utilization. For related information, refer to Quartus® Prime Pro Edition User Guide: Design Optimization .

Table 191.  Maximum Number of DDR4 Interfaces
Device Package Component Interface DIMM Interface
A5EA008B / A5EE008B B23B 2
A5EC008B / A5ED008B B23A 1
B32A 2
M16A 2
A5EC013A / A5ED013A B23A 1
B32A 2
A5EA013B / A5EB013B / A5EE013B B23B 2
A5EC013B ES / A5ED013B ES B23A 1
A5EC013B / A5ED013B B23A 1
B32A 2
M16A 2
A5EC065A / A5ED065A / A5EC052A / A5ED052A B23A 1
B32A 4
A5EC065B / A5ED065B / A5EC052B / A5ED052B B23A 1
B32A 4
A5EC065B ES / A5ED065B ES B23A 1
B32A 4
A5DC064A ES / A5DD064A ES B32A 4 2
A5DC064A / A5DD064A / A5DD051A B32B 4 2

Component Interface refers to x16, x16 + ECC, x32 or x32+ ECC which can be implemented within a single IO96B bank.

1 DIMM interface requires two adjacent IO96B banks located on the same edge of the device; this is supported only on D-Series devices.