External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 1/13/2025
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.5.26. mem_ck_3 for External Memory Interfaces (EMIF) IP - LPDDR4

Clock pin to the memory (channel 3).

Table 129.  Interface: mem_ck_3Interface type: conduit
Port Name Direction Description
mem_3_ck_t Output CK Clock (true) channel 3.
mem_3_ck_c Output CK Clock (complement) channel 3.