22.214.171.124. IP Parameter Configuration
- Debug and Use Reset Request — The Nios V Processor IP Parameter Editor exposes the debug and reset request interface. Depending on your requirement, you can enable these optional interfaces.
- Nios® V Processor Reset Agent and Reset Offset — equivalent to the Nios® II Reset Vector and Reset Offset.
- Nios® V Processor Exception Agent and Offset — You can find these parameters in the BSP Editor.
The default exception region (agent) depends on the largest memory region connected to the Nios® V processor. You can select the .exceptions region using the drop-down list, which is populated from all connected memory regions.
For exception offset, you can configure the Offset (bytes) of the selected region. By default, the exception offset starts at 0. If the exception and reset agent are in the same memory region, the exception offset begins at 32 bytes after the reset offset.
- Caches and Peripheral Regions — equivalent to Nios® II/f Caches and Memory Interfaces. In Nios® V/g processor, you cannot disable, the data and instruction caches. A minimum of 1 Kbyte of cache must be instantiated for both data and instruction lines. Hence, the hardware cannot achieve cache bypass. To bypass the cache when performing transactions with peripherals, you can implement the Nios® V/g processor Peripheral Regions where you can assign these regions to achieve non-cacheable transactions with peripherals.
Note: Select the appropriate size for the caches and peripheral regions. You are required to place all peripherals within the peripheral region for an optimum performance.
- Custom Instructions - Use the Hardware Interface Table and Software C-Macro Table to instantiate the custom instruction.
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