AN 978: Nios® V Processor Migration Guide

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ID 773196
Date 8/22/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Architecture Comparison 3. Processor Core Migration Mapping 4. Design Flow Comparison 5. Migration by Use Case 6. References 7. Document Revision History for AN 978: Nios® V Processor Migration Guide
2. Architecture Comparison x
2.1. Features Comparison 2.2. Ecosystem Comparison
5. Migration by Use Case x
5.1. Migrating Nios® II/e Processor to Nios® V/m Processor 5.2. Migrating Nios® II/f Processor to Nios® V/g Processor 5.3. Timer 5.4. Interrupt 5.5. Ethernet Stack 5.6. Bootloader 5.7. Data and Instruction Cache 5.8. Custom Instructions 5.9. HAL Settings 5.10. Software Packages
5.1. Migrating Nios® II/e Processor to Nios® V/m Processor x
5.1.1. Nios® V Processor Hardware Migration 5.1.2. Nios® V Processor Software Migration
5.1.1. Nios® V Processor Hardware Migration x
5.1.1.1. Processor IP Instantiation in Platform Designer 5.1.1.2. Signal and Interface Mapping 5.1.1.3. IP Parameter Configuration 5.1.1.4. BSP Project Generation
5.1.2. Nios® V Processor Software Migration x
5.1.2.1. Command-Line Build Flow 5.1.2.2. IDE Build Flow
5.2. Migrating Nios® II/f Processor to Nios® V/g Processor x
5.2.1. Nios® V Processor Hardware migration 5.2.2. Nios® V Processor Software Migration
5.2.1. Nios® V Processor Hardware migration x
5.2.1.1. Processor IP Instantiation in Platform Designer 5.2.1.2. Signal and Interface Mapping 5.2.1.3. IP Parameter Configuration 5.2.1.4. BSP Project Generation
5.2.2. Nios® V Processor Software Migration x
5.2.2.1. Command-Line Build Flow 5.2.2.2. IDE Build Flow
1. Overview
2. Architecture Comparison
3. Processor Core Migration Mapping
4. Design Flow Comparison
5. Migration by Use Case
6. References
7. Document Revision History for AN 978: Nios® V Processor Migration Guide

5.2.1.3. IP Parameter Configuration

Figure 6.  Nios® V/g Processor IP Parameter Editor – Part 1
The figure above displays the configuration settings of the Nios® V processor. The following are the parameters that you need to configure:
  • Debug and Use Reset Request — The Nios V Processor IP Parameter Editor exposes the debug and reset request interface. Depending on your requirement, you can enable these optional interfaces.
  • Nios® V Processor Reset Agent and Reset Offset — equivalent to the Nios® II Reset Vector and Reset Offset.
  • Nios® V Processor Exception Agent and Offset — You can find these parameters in the BSP Editor.

    The default exception region (agent) depends on the largest memory region connected to the Nios® V processor. You can select the .exceptions region using the drop-down list, which is populated from all connected memory regions.

    For exception offset, you can configure the Offset (bytes) of the selected region. By default, the exception offset starts at 0. If the exception and reset agent are in the same memory region, the exception offset begins at 32 bytes after the reset offset.

Figure 7. Linker Section Mappings
Figure 8. Linker Memory Regions
Figure 9.  Nios® V/g Processor IP Parameter Editor – Part 2
  • Caches and Peripheral Regions — equivalent to Nios® II/f Caches and Memory Interfaces. In Nios® V/g processor, you cannot disable, the data and instruction caches. A minimum of 1 Kbyte of cache must be instantiated for both data and instruction lines. Hence, the hardware cannot achieve cache bypass. To bypass the cache when performing transactions with peripherals, you can implement the Nios® V/g processor Peripheral Regions where you can assign these regions to achieve non-cacheable transactions with peripherals.
    Note: Select the appropriate size for the caches and peripheral regions. You are required to place all peripherals within the peripheral region for an optimum performance.
Figure 10.  Nios® V/g Processor IP Parameter Editor – Part 3
  • Custom Instructions - Use the Hardware Interface Table and Software C-Macro Table to instantiate the custom instruction.
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