AN 978: Nios® V Processor Migration Guide

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ID 773196
Date 8/22/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Architecture Comparison 3. Processor Core Migration Mapping 4. Design Flow Comparison 5. Migration by Use Case 6. References 7. Document Revision History for AN 978: Nios® V Processor Migration Guide
2. Architecture Comparison x
2.1. Features Comparison 2.2. Ecosystem Comparison
5. Migration by Use Case x
5.1. Migrating Nios® II/e Processor to Nios® V/m Processor 5.2. Migrating Nios® II/f Processor to Nios® V/g Processor 5.3. Timer 5.4. Interrupt 5.5. Ethernet Stack 5.6. Bootloader 5.7. Data and Instruction Cache 5.8. Custom Instructions 5.9. HAL Settings 5.10. Software Packages
5.1. Migrating Nios® II/e Processor to Nios® V/m Processor x
5.1.1. Nios® V Processor Hardware Migration 5.1.2. Nios® V Processor Software Migration
5.1.1. Nios® V Processor Hardware Migration x
5.1.1.1. Processor IP Instantiation in Platform Designer 5.1.1.2. Signal and Interface Mapping 5.1.1.3. IP Parameter Configuration 5.1.1.4. BSP Project Generation
5.1.2. Nios® V Processor Software Migration x
5.1.2.1. Command-Line Build Flow 5.1.2.2. IDE Build Flow
5.2. Migrating Nios® II/f Processor to Nios® V/g Processor x
5.2.1. Nios® V Processor Hardware migration 5.2.2. Nios® V Processor Software Migration
5.2.1. Nios® V Processor Hardware migration x
5.2.1.1. Processor IP Instantiation in Platform Designer 5.2.1.2. Signal and Interface Mapping 5.2.1.3. IP Parameter Configuration 5.2.1.4. BSP Project Generation
5.2.2. Nios® V Processor Software Migration x
5.2.2.1. Command-Line Build Flow 5.2.2.2. IDE Build Flow
1. Overview
2. Architecture Comparison
3. Processor Core Migration Mapping
4. Design Flow Comparison
5. Migration by Use Case
6. References
7. Document Revision History for AN 978: Nios® V Processor Migration Guide

1. Overview

This application note is a fundamental guide for you to get started with building a Nios® V processor system and running a simple Hello World software. The target boards are the Intel FPGA development kits. The build software includes both Intel® Quartus® Prime software and Ashling* RiscFree* IDE for Intel® FPGAs.
The document provides the following information:
  • Introduces you to the basic design flow for the Nios® V processor.
  • Provides instructions on how to generate a Nios® V example design, create a software program, and run the program on an Intel FPGA device.
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