AN 978: Nios® V Processor Migration Guidelines

ID 773196
Date 5/15/2024
Document Table of Contents Software Component

The software development flow starts with the creation of board support package (BSP) and application (APP). Altera recommends creating a software folder with app and bsp sub-folders inside your Quartus® Prime project directory. Nios® II processor software also has the same file organization.
Figure 3.  Nios® V Processor Software Project File Directory
Note: Generated Nios® II processor software files are not compatible with the Nios® V processor. You need to regenerate the Nios® V processor BSP and APP project.

Nios® V Processor BSP Regeneration

  1. Open the BSP Editor in Nios® V Command Shell with the command niosv-bsp-editor.
  2. Select the design SOPCINFO file in the SOPC Information File field, then click OK.
  3. The window assigns BSP target directory and BSP Settings File name to default locations.
    Figure 4. New BSP Window
  4. Apply the same Nios® II processor BSP settings into the Nios® V processor BSP setting. Refer to Intel HAL Settings to migrate the BSP Settings.
    Figure 5.  Nios® V Processor BSP Settings
  5. Select the appropriate memory region for exception vector in BSP Editor > Linker Script.
    Figure 6. Linker Script
  6. Click Generate BSP to create a new BSP project for Nios® V processor.

Nios® V Processor APP Regeneration

  1. Copy the Nios® II application source codes into the APP folder.
  2. Start the Nios V Command Shell.
  3. Run niosv-app command to create an APP CMakeLists.txt file.
    niosv-app -b=<BSP directory> -a=<APP directory> -s=<Nios II application source codes>
  4. Run CMake executable.
    cmake -B <APP directory>/build -S <APP directory> -G “Unix Makefiles”
  5. Run Make executable. After successful Make, the Nios® V processor software ELF file is located in the <APP directory>/build folder.
    make -C <APP directory>/build
  6. Download the software ELF file into the Nios® V processor system.
    niosv-download <Nios V ELF file>
  7. Open JTAG UART terminal to print the Hello World message.

Alternatively, you can use Ashling* RiscFree* IDE for Intel® FPGAs for Nios® V processor software development. After the BSP creation and APP creation, you can import both folder into the workspace of Ashling* RiscFree* IDE for Intel® FPGAs to continue.