AN 978: Nios® V Processor Migration Guidelines

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ID 773196
Date 5/22/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Architecture Comparison 3. Processor Core Upgrade Paths 4. Design Flow Comparison 5. Processor Core Comparison 6. Feature Comparison 7. Assembly Language Comparison 8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines
2. Architecture Comparison x
2.1. Features Comparison 2.2. Ecosystem Comparison 2.3. Software Optimization
4. Design Flow Comparison x
4.1. Differences in the Design Flow 4.2. Design Upgrade from Nios® II Processor to Nios® V Processor
4.2. Design Upgrade from Nios® II Processor to Nios® V Processor x
4.2.1. Quartus® Prime Standard Edition 4.2.2. Quartus® Prime Pro Edition
4.2.1. Quartus® Prime Standard Edition x
4.2.1.1. Hardware Component 4.2.1.2. Software Component
4.2.2. Quartus® Prime Pro Edition x
4.2.2.1. Hardware Component 4.2.2.2. Software Component
5. Processor Core Comparison x
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor 5.2. Upgrading Nios® II Processor to Nios® V/m Processor 5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor x
5.1.1. Hardware Perspective 5.1.2. Software Perspective
5.1.1. Hardware Perspective x
5.1.1.1. Signal and Interface Mapping 5.1.1.2. IP Parameter Configuration 5.1.1.3. BSP Project Generation
5.1.2. Software Perspective x
5.1.2.1. Command-Line Build Flow 5.1.2.2. IDE Build Flow
5.2. Upgrading Nios® II Processor to Nios® V/m Processor x
5.2.1. Hardware Perspective 5.2.2. Software Perspective
5.2.1. Hardware Perspective x
5.2.1.1. Signal and Interface Mapping 5.2.1.2. IP Parameter Configuration 5.2.1.3. BSP Project Generation
5.2.2. Software Perspective x
5.2.2.1. Command-Line Build Flow 5.2.2.2. IDE Build Flow
5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor x
5.3.1. Hardware Perspective 5.3.2. Software Perspective
5.3.1. Hardware Perspective x
5.3.1.1. Signal and Interface Mapping 5.3.1.2. IP Parameter Configuration 5.3.1.3. BSP Project Generation
5.3.2. Software Perspective x
5.3.2.1. Command-Line Build Flow 5.3.2.2. IDE Build Flow
6. Feature Comparison x
6.1. Timer 6.2. Interrupt 6.3. Shadow Register 6.4. Ethernet Stack 6.5. Bootloader 6.6. Data and Instruction Cache 6.7. Tightly Coupled Memory 6.8. Custom Instructions 6.9. Error Correction Code 6.10. Altera HAL Settings 6.11. Micrium MicroC/OS-II BSP Settings 6.12. Software Packages
7. Assembly Language Comparison x
7.1. Arithmetic and Logic Operations 7.2. Data Handling and Memory Operations 7.3. Control Flow Operations 7.4. Miscellaneous Operations
1. Overview
2. Architecture Comparison
3. Processor Core Upgrade Paths
4. Design Flow Comparison
5. Processor Core Comparison
6. Feature Comparison
7. Assembly Language Comparison
8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines

6.4. Ethernet Stack

Nios® V processor supports MicroC/TCP-IP protocol stack and it is not compatible with the retired Nios II Nichestack Ethernet Stack. You may use Altera-provided uC/TCP-IP design examples as baseline and port over other peripherals.

Note: Altera recommends re-instantiating the Triple Speed Ethernet IP and DMA Controller IP when upgrading from the Nios® II Processor to the Nios® V Processor.
Table 29.  Board Specific Configuration
Soft IPs Nios® V Processor Nios® II Processor
DMA Controller
  • Only support mSGDMA for both Quartus® Prime Standard Edition and Quartus® Prime Pro Edition
  • Enable extended feature support
  • Quartus® Prime Standard Edition supports
    • SGDMA
    • mSGDMA
  • Quartus® Prime Pro Edition supports mSGDMA only
  • Disable extended feature support
Table 30.  BSP Settings
BSP Settings Nios® II Processor Nios® V Processor
cflag_defined_symbols -DTSE_MY_SYSTEM -DTSE_MY_SYSTEM -DALT_DEBUG
cflag_warning -Wall -Wall -Wformat -Wformat-security
enable_cflag_fstack_protector_strong - Enable
enable_cflag_wformat_security - Enable
Enable JTAG UART small driver Disable Enable
DHCP Client Enable in BSP Editor Enable in application
Static IP Address
  • Disable DHCP Client in BSP Editor
  • Set static IP address in application
  • Disable DHCP Client in application
  • Set static IP address in application
Software package altera_iniche uc_tcp_ip
ucosii.os_tmr_en Disable Enable
ucosii.os_max_event 60 80
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