AN 978: Nios® V Processor Migration Guidelines

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ID 773196
Date 5/22/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Architecture Comparison 3. Processor Core Upgrade Paths 4. Design Flow Comparison 5. Processor Core Comparison 6. Feature Comparison 7. Assembly Language Comparison 8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines
2. Architecture Comparison x
2.1. Features Comparison 2.2. Ecosystem Comparison 2.3. Software Optimization
4. Design Flow Comparison x
4.1. Differences in the Design Flow 4.2. Design Upgrade from Nios® II Processor to Nios® V Processor
4.2. Design Upgrade from Nios® II Processor to Nios® V Processor x
4.2.1. Quartus® Prime Standard Edition 4.2.2. Quartus® Prime Pro Edition
4.2.1. Quartus® Prime Standard Edition x
4.2.1.1. Hardware Component 4.2.1.2. Software Component
4.2.2. Quartus® Prime Pro Edition x
4.2.2.1. Hardware Component 4.2.2.2. Software Component
5. Processor Core Comparison x
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor 5.2. Upgrading Nios® II Processor to Nios® V/m Processor 5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor x
5.1.1. Hardware Perspective 5.1.2. Software Perspective
5.1.1. Hardware Perspective x
5.1.1.1. Signal and Interface Mapping 5.1.1.2. IP Parameter Configuration 5.1.1.3. BSP Project Generation
5.1.2. Software Perspective x
5.1.2.1. Command-Line Build Flow 5.1.2.2. IDE Build Flow
5.2. Upgrading Nios® II Processor to Nios® V/m Processor x
5.2.1. Hardware Perspective 5.2.2. Software Perspective
5.2.1. Hardware Perspective x
5.2.1.1. Signal and Interface Mapping 5.2.1.2. IP Parameter Configuration 5.2.1.3. BSP Project Generation
5.2.2. Software Perspective x
5.2.2.1. Command-Line Build Flow 5.2.2.2. IDE Build Flow
5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor x
5.3.1. Hardware Perspective 5.3.2. Software Perspective
5.3.1. Hardware Perspective x
5.3.1.1. Signal and Interface Mapping 5.3.1.2. IP Parameter Configuration 5.3.1.3. BSP Project Generation
5.3.2. Software Perspective x
5.3.2.1. Command-Line Build Flow 5.3.2.2. IDE Build Flow
6. Feature Comparison x
6.1. Timer 6.2. Interrupt 6.3. Shadow Register 6.4. Ethernet Stack 6.5. Bootloader 6.6. Data and Instruction Cache 6.7. Tightly Coupled Memory 6.8. Custom Instructions 6.9. Error Correction Code 6.10. Altera HAL Settings 6.11. Micrium MicroC/OS-II BSP Settings 6.12. Software Packages
7. Assembly Language Comparison x
7.1. Arithmetic and Logic Operations 7.2. Data Handling and Memory Operations 7.3. Control Flow Operations 7.4. Miscellaneous Operations
1. Overview
2. Architecture Comparison
3. Processor Core Upgrade Paths
4. Design Flow Comparison
5. Processor Core Comparison
6. Feature Comparison
7. Assembly Language Comparison
8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines

2.2. Ecosystem Comparison

Table 3.  Integrated Development Environment (IDE) and Software Ecosystem Comparison
Features Ashling* Visual Studio Code Extension for Altera FPGAs Ashling* RiscFree* IDE for Altera® FPGAs Nios® II Embedded Design Suite
IDE type Visual Studio Code based Eclipse based Eclipse based
Toolchain GNU RISC-V Embedded GCC Toolchain GNU RISC-V Embedded GCC Toolchain GNU GCC Toolchain
Automated scan chain Yes Yes Yes
Core support Nios® V processor (Risc-V), ARM Cortex-A9, A53 Nios® V processor (Risc-V), ARM Cortex-A9, A53 Nios® II only
Heterogeneous debug Yes Yes No
Trace1 No On-chip Trace: ARM Cortex-A9, A53 No
Baremetal debug Yes Yes Yes
uC/OS-II debug No Yes (With OS awareness) Yes (Without OS awareness)
FreeRTOS* debug Yes Yes (With OS awareness) No
Zephyr* debug Yes Yes (With OS awareness) No
1 Nios® V processor does not support trace feature.
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