AN 978: Nios® V Processor Migration Guidelines

ID 773196
Date 5/15/2024
Document Table of Contents Hardware Component

If you compile your design using Quartus® Prime Pro Edition, you can start the migration from Platform Designer. The following figure shows an example of the Nios® II Processor QSYS design.

  1. Right-click Nios II Processor in the Description column, and select Replace.
    Figure 7.  Nios II Processor Qsys Design
  2. Search for Nios® V processor from the Replace Instance. Select your preferred processor core.
  3. Double-click on your selected Nios® V processor IP. The parameters window appears.
  4. Select Enable Reset from Debug Module and click Finish.
  5. In the Connection Migration Tool > Interface mapper, reconnect:
    • data_master to data_manager
    • instruction_master to instruction_manager
    • debug_mem_slave to dm_agent
  6. Click OK. Nios® V processor replaces Nios® II processor.
    Figure 8. Interface Mapper
    Figure 9. Old and New System Connections
  7. Proceed to establish the following connections:
    • Disconnect dbg_reset_out to reset
    • Connect dbg_reset_out to ndm_reset_in
  8. Next, verify the connections based on the table below:
    Table 8.   Nios® V Processor to Nios® II Processor Interfaces
    Interface Nios® V Processor Nios® II Processor Description
    Clock clock clock Similar clock input
    Reset reset reset Similar hard reset
    Debug reset
    • dbg_reset_out
    • ndm_reset_in
    debug_reset_request Mainly used to issue debug reset from CLI or IDE. By default, this feature is enabled in Nios® II/e processor but disabled in Nios® V/m processor.
    Interrupts platform_irq_rx irq Nios® II/e processor supports 32 platform interrupts. Nios® V/m processor supports 16 platform interrupts.
    Timer and Software Interrupt Module timer_sw_agent N/A Only supported in Nios® V processor. By default, it is connected to the data manager.
    Debug dm_agent debug_mem_slave Allow JTAG download and debug. For Nios® V/m processor, it is connected to the data manager and instruction manager by default.
    Data bus data_manager data_master
    • Nios® II/e processor uses Avalon® memory-mapped interface.
    • Nios® V/m processor uses Arm* AMBA* AXI-4 Lite.
    Instruction bus instruction_manager instruction_master
    • Nios® II/e processor uses Avalon memory-mapped interface.
    • Nios® V/m processor uses Arm AMBA AXI-4 Lite.
  9. Open your selected Nios® V processor IP, click Vectors > Reset Agent, and update the parameters as onchip_memory2_0.s1.
  10. Rename the processor core to niosv. A preview of the final system is shown below.
    Figure 10.  Nios® V Processor System

You can now generate the system HDL and compile Quartus® Prime Project. Use the Quartus® Prime Programmer software to configure the design SOF file for design verification.