Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

ID 741330
Date 10/02/2023

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 23.3
IP Version 22.1.0

The Triple-Speed Ethernet Intel® FPGA IP for Intel Agilex® 7 provides the capability of generating design examples for selected configurations, which allows you to:

  • Compile the design to get an estimate of the IP area usage and timing.
  • Simulate the design to verify the IP functionality through simulation.
  • Test the design on the hardware using the Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit.
When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Figure 1. Development Stages for the Design Example