Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

ID 741330
Date 10/02/2023

2.3.1. Design Components

Table 5.  Design Components
Component Description
Triple-Speed Ethernet Intel® FPGA IP

The Triple-Speed Ethernet Intel® FPGA IP (altera_eth_tse) is instantiated with the following configuration:

  • Core Configurations:
    • Core Variation: 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII PCS
    • Use internal FIFO: Not selected
    • Number of ports: 4
    • Transceiver type: LVDS I/O
  • MAC Options:
    • Enable MAC 10/100 half duplex support: Selected
    • Enable local loopback on MII/GMII: Selected
    • Enable supplemental MAC unicast addresses: Not selected
    • Include statistics counters: Selected
    • Enable 64-bit statistics byte counters: Not selected
    • Include multicast hashtable: Not selected
    • Align packet headers to 32-bit boundary: Not selected
    • Enable full-duplex flow control: Selected
    • Enable VLAN detection: Not selected
    • Enable magic packet detection: Selected
    • Include MDIO module (MDC/MDIO): Selected
    • Host clock divisor: 50
  • Timestamp Options:
    • Enable timestamping: Not selected
  • PCS/Transceiver Options:
    • Enable SGMII bridge: Selected
Client Logic Generates and monitors packets sent or received through the IP.
Ethernet Traffic Controller Controlled via Avalon® memory-mapped interface.
JTAG to Avalon® memory-mapped interface Address Decoder Convert JTAG Signals for Avalon® memory-mapped interface.