Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

ID 741330
Date 10/02/2023

1.4. Compiling and Configuring the Design Example in Hardware

To compile the hardware design example and configure it on your Intel Agilex® 7 device, follow these steps:

  1. Ensure hardware design example generation is complete.
  2. In the Intel® Quartus® Prime Pro Edition software, open the Intel® Quartus® Prime project <design_example_dir>/hardware_test_design/altera_eth_tse_hw.qpf .
  3. On the Processing menu, click Start Compilation.
  4. After a successful compilation, a.sof file is available in <design_example_dir>/hardwarde_test_design directory. Follow these steps to program the hardware design example on the Intel Agilex® 7 device:
    1. On the Tools menu, click Programmer.
    2. In the Programmer, click Hardware Setup.
    3. Select a programming device.
    4. Select and add the Agilex 7 I-Series Transceiver-SoC Development Kit to which your Intel® Quartus® Prime Pro Edition session can connect.
    5. Ensure that Mode is set to JTAG.
    6. Select the device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    7. In the row with your .sof, check the box for the .sof.
    8. Check the box in the Program/Configure column.
    9. Click Start.