Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

ID 741330
Date 10/02/2023

2.7. Hardware Limitations

  • The design example supports only two ports that can be tested with FMC loopback. The pin assignments is based on the soft-CDR mode pin location limitations and loopback mapping.
  • There are 2 .sof files with 2 ports with FMC loopback. In both cases, there are 2 ports left unconnected. You need to manually edit the .qsf file to generate 2 .sof files.
  • To test the traffic in Port 2 & 3, swap the pin constraints in the generated .qsf file with Port 0 & 1. Generate the .sof file after swapping the pin constraints.
  • Although there are 16 LVDS pin pairs broken to FMC connector, you can only use 2 ports as the other ports are split between the top and bottom of bank 3B.