Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

ID 741330
Date 10/02/2023

2.1. Features

  • Generates the design example for Triple-Speed Ethernet Multiport Ethernet MAC without Internal FIFO and PCS with LVDS I/O using multi-channel shared FIFO.
  • Generates traffic at the transmit path and validates received data through the transceiver LVDS I/O external loopback.
  • TX and RX serial loopback mode.
  • Supports only external loopback.
  • Supports only two ports.
  • Supports packet statistics report on both MAC transmitter and MAC receiver.
  • Supports System Console user interface. You can make use of the TCL-based user interface to dynamically configure and monitor any registers in this design example.
  • Basic packet checking capabilities of traffic monitor.