Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

ID 741330
Date 10/02/2023

2.5.2. Design Constraints

The following is the current constraint statements in the project .qsf file:
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE ED8401
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-13"
You must replace the constraint statements in the project .qsf file if you are using the following version of the Intel Agilex® 7 I-Series Transceiver SoC development kit:
Table 7.  Required Design Constraint Statements in the Project .qsf
Serial Number ID Constraint Statements Required in the Project .qsf Action Required
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTC3888 
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
Replace the current constraints in the QSF file with these constraints.

Refer to Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide for more information on the Intel Agilex® 7 I-Series Transceiver-SoC development kit and their respective serial number identifier.