Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

Download PDF
ID 741330
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA 3. Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide Archive 4. Document Revision History for the Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Hardware Limitations
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clock and Reset Signals
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Test Procedure 2.5.2. Design Constraints
1. Quick Start Guide
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA
3. Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide Archive
4. Document Revision History for the Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

2.5.2. Design Constraints

The following is the current constraint statements in the project .qsf file: 
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE ED8401
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-13"
You must replace the constraint statements in the project .qsf file if you are using the following version of the Intel Agilex® 7 I-Series Transceiver SoC development kit:
Table 7.  Required Design Constraint Statements in the Project .qsf
Serial Number ID Constraint Statements Required in the Project .qsf Action Required
2000001 
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTC3888 
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
 Replace the current constraints in the QSF file with these constraints.

Refer to Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide for more information on the Intel Agilex® 7 I-Series Transceiver-SoC development kit and their respective serial number identifier.

Related Information
Level Two Title