Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

ID 741330
Date 10/02/2023

2.4. Simulation

The simulation test case performs the following steps:
  1. Starts up the design example with an operating speed of 1G.
  2. Configures the Triple-Speed Ethernet MAC and PCS registers.
  3. Waits until the assertion of the measure valid signal.
  4. Sends non-PTP packets to port 0.
  5. MAC RX port 0 sends the received packets to MAC TX port 1.

When simulation ends, the values of the MAC statistics counters for port 3 are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon® streaming interface received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters of port 3 are equal to the TX MAC statistics counters of port 0.