Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

ID 741330
Date 10/02/2023

2.5.1. Test Procedure

After you compile the Triple-Speed Ethernet Intel® FPGA IP design example and configure it on your Intel Agilex® 7 device, you can use the System Console to program the IP.

To turn on the System Console and test the hardware design example, follow these steps:

  1. In the Intel® Quartus® Prime Pro Edition software, select Tools > System Debugging Tools>System Console to launch the system console.
  2. In the Tcl Console pane, type cd hwtest/agx to change directory to <design_example_dir>/hardware_test_design/hwtest/agx/lvdsio/.
  3. Type source basic/basic.tcl.
  4. Type list_jtag to display a list of JTAG master indexes that are connected to your board.
  5. Type set_jtag<number_of appropriate_JTAG_master> to select the JTAG master.
  6. Type source hwtest_main.tcl for port 0 and 1 or source hwtest_main_2.tcl for port 2 and 3 to run the design example in 10 Mbps, 100 Mbps and 1 Gbps Ethernet speed.
A successful test run displays the following message: