Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

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ID 741330
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA 3. Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide Archive 4. Document Revision History for the Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Hardware Limitations
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clock and Reset Signals
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Test Procedure 2.5.2. Design Constraints
1. Quick Start Guide
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA
3. Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide Archive
4. Document Revision History for the Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

2.5.1. Test Procedure

After you compile the Triple-Speed Ethernet Intel® FPGA IP design example and configure it on your Intel Agilex® 7 device, you can use the System Console to program the IP.

To turn on the System Console and test the hardware design example, follow these steps:

  1. In the Intel® Quartus® Prime Pro Edition software, select Tools > System Debugging Tools>System Console to launch the system console.
  2. In the Tcl Console pane, type cd hwtest/agx to change directory to <design_example_dir>/hardware_test_design/hwtest/agx/lvdsio/.
  3. Type source basic/basic.tcl.
  4. Type list_jtag to display a list of JTAG master indexes that are connected to your board.
  5. Type set_jtag<number_of appropriate_JTAG_master> to select the JTAG master.
  6. Type source hwtest_main.tcl for port 0 and 1 or source hwtest_main_2.tcl for port 2 and 3 to run the design example in 10 Mbps, 100 Mbps and 1 Gbps Ethernet speed.
A successful test run displays the following message:
Level Two Title