Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

ID 741330
Date 10/02/2023

1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench

Figure 5. Procedure to Simulate Example Testbench
Follow these steps to simulate the testbench:
  1. Change to the testbench simulation directory <design_example_dir>/example_testbench.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Testbench.
    Table 4.  Steps to Simulate the Testbench
    Simulator Instructions
    ModelSim* In the command line, type vsim -do If you prefer to simulate without bringing up the ModelSim* GUI, type vsim -c -do
    Synopsys* VCS* / VCS* MX In the command line, type sh or sh
    Xcelium* In the command line, type sh
  3. Analyze the results. The successful testbench sends ten packets, receives the same number of packets, and displays the following message:
End of Simulation - Break